LEE Flash G1
Product Info
LEE Flash G1,best fit eFlash to BCD process
LEE Flash G1 (G1) is based on simple SONOS architecture and capable to scale down to 40nm geometry and supports auto grade temperature and quality.
G1 is cost effective Flash solution up for medium memory capacity requirement up to several 100KBytes.
G1 also allows user to re-use IPs and Macros developed for standard CMOS platform because the adoption of G1 process module does not change characteristics of the logic transistors and SPICE model.
Major Features
- Supports high temperature and long retention life time for severe automotive requirement
- Low power in Program/Erase operation for power critical applications
- Requires few (2~3) additional masks
- No change to SPICE model of Standard CMOS process, for re-using existing design and IP
- Short Test and Bake time to reduce chip cost
Sample Spec
| Item | Spec |
|---|---|
| Process platform | 130BCD |
| Memory Size | 64 Kbyte |
| Data Bus(Main) | 32 I/O |
| P/E Cycles | 100k |
| Supply Voltage | VDD 1.5V±10% |
| VCC 2.5V~5.5V | |
| Additional Masks | 2~3 |
| Operation Temperature(Tj) | -40~175℃ |
| Data Retention | 10years@175℃ post PE 10K |
High Temperature Operation
SONOS is the device which enables memory functionality trapping electrons in Silicon Nitride film, and the retention life is controlled by optimization of thickness and film properties of oxide and Silicon Nitride films.The data retention characteristics of G1 have been confirmed to be @200°C for more than 10 years.
Large Programming Size enables Short Testing Time
G1 uses FN tunneling technology to achieve extremely low power in program and erase.
It consumes 1/1,000,000 times current, compare to conventional technologies using hot carrier injection for Program/Erase operation.
This also helps reducing testing time, which dominates large portion of the chip cost.
Low Cost
Short Test Time: G1 achieves very short test time for two reasons.
- Extremely low power in Program/Erase allows tester to Program/Erase the whole memory mat at once, compare to conventional solution Program/Erase smaller sections for many times to Program/Erase the whole memory mat.
- Sharp Vt distribution in programming will eliminate the requirement for multiple programming and verification, so that programming operation always completes at one time, not in multiple steps, to dramatically reduce programming time.
Short Baking Time
Floadia’s unique memory architecture simplifies Life Time Prediction of the memory cell, which allows chip company to screen devices with shorter baking time.
2-3 Mask adder
G1 requires only 2 to 3 additional masks on standard CMOS process, reducing expensive mask cost to implement NVM feature on your chip. Conventional solution will usually take around 10+ additional masks and uses special manufacturing process.
Re-use of existing IP asset
Unlike normal Flash IPs, our Flash IP does not affect SPICE model of the logic transistors, which means you can utilize existing IPs and assets that has been developed, and will eliminate additional IP investment specific for Flash ICs.
Track Record
| Manufacturing status | Item |
|---|---|
| Mass Production | 130nm, PSMC 90nm |
| Available on | TSMC 130BCD+ |
| Under development | PSMC 80BCD, SMIC 90BCD, UMC 110BCD |
